The present invention relates to a method and apparatus for current-to-voltage conversion which is able to provide sensitive current-to-voltage detection for a small amplitude AC current signal, even if the AC current signal has a DC component which varies greatly over a very wide range.
Existing approaches to current-to-voltage conversion in VLSI are usually based on:
(1) Charge integration. A current charging or discharging a capacitor during a given period transduces itself linearly into a voltage. This process introduces a delay that is the time required for the charge integration and is inversely proportional to the current. The dynamic range of the input current is usually below three decades. Moreover, the capacitor is a critical device as its capacitance should be voltage-independent.
(2) Characteristic of drain-to-source voltage versus drain current of a MOS transistor biased in the triode region. The equivalent resistance in this region is almost constant when the drain-to-source voltage is small, so it can be used for a linear current-to-voltage conversion. The conversion gain (output voltage over input current) is low, about a couple of milli-volts per micro-ampere. Thus, an input current varying in a nano-ampere range cannot be correctly converted. Furthermore, as the output voltage signal is small, an amplifier is usually required.
(3) Characteristic of gate-to-source voltage versus drain current of a MOS transistor biased in the saturation region. This feature makes a logarithmic conversion. The conversion gain of a logarithmic converter is of the order of one hundred millivolts per decade of current. Moreover, the logarithmic compression reduces the chance to detect current derivatives.
Accordingly, an object of the present invention is to provide a method and circuit for the realization of a highly sensitive current detector operational in a very wide dynamic range and capable of performing linear and high-gain current-to-voltage conversions. The detection can be done in a linear and a non-linear mode of operation of the circuit, combining the advantages of high-gain in a linear conversion and large dynamic range in a logarithmic conversion in one circuit.
Another object of the invention is to provide a circuit with a simple structure composed of a minimum number of transistors on-chip for efficient current to voltage conversion. The circuit does not require any off-chip capacitors or resistors, and is capable of operating in a linear mode on a single clock.
Yet another object of the current invention is to introduce minimal delay into a current-to-voltage conversion, while allowing an input current varying in a nano-ampere, or even sub-nano, range to be correctly converted.
In accordance with a first aspect of the present invention, there is provided a method for adapting a three-terminal semiconductor device having an operating point and used for current-to-voltage conversion, to a variation of input current level in order to maintain the operation of the device in the linear portion of a curve belonging to a family of i-v curves selected in response to a bias voltage and comprising a linear and a non-linear portion. The three-terminal semiconductor device has an input current terminal, a bias terminal, and a common terminal. A bias voltage between the bias terminal and common terminal controls the current flow between the input current terminal and the common terminal.
The method comprises steps of setting the bias voltage to a preset value in order to position the operating point of the device to an initial value, detecting a change in level of the direct current component of an input current, and adjusting the bias voltage value in response to the change in current level in order to adapt the operating point of the device to an alternate i-v curve so as to remain in the linear portion of a curve.
The current IIN of the device can be set so as to maximize the range of output voltage VOUT by situating the operating point at approximately the middle of the saturation region. Setting the bias voltage to a preset value to position the operating point can be done using a structure of two cascoded transistors, one of which is drain-gate shorted, to sample an input current.
The step of detecting a change in level of an input current can be done upon closing of a switch and the bias voltage of the semiconductor device is adjusted with respect to a newly sampled input current.
In accordance with a second aspect of the present invention, there is provided a circuit to perform current-to-voltage conversion comprising a three-terminal semiconductor device, having an input current terminal, a bias terminal, and a common terminal. A bias voltage between the bias terminal and common terminal controls the current flow between the input current terminal and the common terminal, whereby the output voltage to be measured is present at the input current terminal. The device has an operating point situated on a curve belonging to a family of i-v curves, the curves comprising a linear and a non-linear portion. The circuit also comprises circuitry to detect a level of an input current, and circuitry to adjust the bias voltage value in response to the input current level detected.
More specifically, this can be done by connecting a structure of two cascoded transistors, one of which is drain-gate shorted, to the bias voltage terminal of the three-terminal semiconductor device, and to a clocked transistor, which is connected to the input current terminal of the semiconductor device.
As an alternative, logarithmic mode can also be achieved by simply replacing the clocked transistor by a wire, an off-chip resistance, or a logic gate using a voltage-controlled switch. It is preferable for the entire circuit to reside on an integrated circuit chip but this does not exclude the possibility of having off-chip components.